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K7R323682C K7R321882C K7R320982C
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
36Mb QDRII SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
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* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C Document Title
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Put the data in the table of DC Characteristics, Pin Capacitance and Thermal Resistance. 1. Add 300MHz Bin 2. Change AC Characteristics. 1. Change Samsung JEDEC Code in ID REGISTER DEFINITION 1. Final 2. Change Vss/SA to NC/SA in Pin Configuration 1. Correct typo Draft Date Jan. 17, 2006 Apr. 26, 2006 Remark Advance Preliminary
0.2
May. 04, 2006
Preliminary
0.3 1.0
Jun. 05, 2006 Jul. 10, 2006
Preliminary Final
1.1
Aug. 23, 2006
Final
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM
FEATURES
* 1.8V+0.1V/-0.1V Power Supply. * DLL circuitry for wide output data valid window and future frequency scaling. * I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O. * Separate independent read and write data ports with concurrent read and write operation * HSTL I/O * Full data coherency, providing most current data. * Synchronous pipeline read with self timed early write. * Registered address, control and data input/output. * DDR (Double Data Rate) Interface on read and write ports. * Fixed 2-bit burst for both read and write operation. * Clock-stop supports to reduce current. * Two input clocks (K and K) for accurate DDR timing at clock rising edges only. * Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. * Two echo clocks (CQ and CQ) to enhance output data traceability. * Single address bus. * Byte write (x9, x18, x36) function. * Separate read/write control pin (R and W) * Simple depth expansion with no data contention. * Programmable output impedance. * JTAG 1149.1 compatible test access port. * 165FBGA(11x15 ball array FBGA) with body size of 15x17mm & Lead Free Org. Part Number K7R323682C-F(E)C(I)30 X36 K7R323682C-F(E)C(I)25 K7R323682C-F(E)C(I)20 K7R321882C-F(E)C(I)30 X18 K7R321882C-F(E)C(I)25 K7R321882C-F(E)C(I)20 K7R320982C-F(E)C(I)30 X9 K7R320982C-F(E)C(I)25 K7R320982C-F(E)C(I)20 Cycle Time 3.3 4.0 5.0 3.3 4.0 5.0 3.3 4.0 5.0 Access Unit Time 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 ns ns ns ns ns ns ns ns ns
* -F(E)C(I) F(E) [Package type]: E-Pb Free, F-Pb C(I) [Operating Temperature]: C-Commercial, I-Industrial
FUNCTIONAL BLOCK DIAGRAM
36 (or 18) DATA REG
D (Data in)
36 (or 18) 19 (or 20) WRITE/READ DECODE
36 (or 18)
WRITE DRIVER
ADDRESS
19 (or 20)
ADD REG
OUTPUT SELECT
R W BWX
4(or 2)
CTRL LOGIC
1Mx36 (2Mx18) MEMORY ARRAY
SENSE AMPS
OUTPUT REG
72 (or 36)
72 (or 36)
OUTPUT DRIVER
36 (or 18) Q(Data Out) CQ, CQ
K K C C
(Echo Clock out)
CLK GEN SELECT OUTPUT CONTROL
Notes: 1. Numbers in ( ) are for x18 device, x9 device also the same with appropriate adjustments of depth and width.
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 Doff D31 Q32 Q33 D33 D34 Q35 TDO 2 NC/SA* Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 NC/SA* D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA 10 NC/SA* Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
PIN CONFIGURATIONS(TOP VIEW) K7R323682C(1Mx36)
Notes: 1. * Checked No Connect (NC) or Vss pins are reserved for higher density address, i.e. 3A for 72Mb, 10A for 144Mb and 2A for 288Mb. 2. BW0 controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls write to D27:D35.
PIN NAME
SYMBOL K, K C, C CQ, CQ Doff SA D0-35 PIN NUMBERS 6B, 6A 6P, 6R 11A, 1A 1H 9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R 10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L 9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N 1C,1D,2E,1G,1J,2K,1M,1N,2P 11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L 9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N 3P,1B,2C,1E,1F,2J,1K,1L,2M,1P 4A 8A 7B,7A,5A,5B 2H,10H 11H 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M, 8M,4N,8N 10R 11R 2R 1R 2A,3A,10A, DESCRIPTION Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs 1 NOTE
Q0-35 W R BW0, BW1,BW2, BW3 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC
Data Outputs Write Control Pin, active when low Read Control Pin, active when low Block Write Control Pin, active when low Input Reference Voltage Output Driver Impedance Control Input Power Supply (1.8 V) Output Power Supply (1.5V or 1.8V) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test Data Output No Connect 3 2
Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 NC/SA* Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 SA D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 NC/SA* NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
PIN CONFIGURATIONS(TOP VIEW) K7R321882C(2Mx18)
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb. 2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.
PIN NAME
SYMBOL K, K C, C CQ, CQ Doff SA D0-17 Q0-17 W R BW0, BW1 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC PIN NUMBERS 6B, 6A 6P, 6R 11A, 1A 1H 3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R 10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D, 3F,2G,3J,3L,3M,2N 11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E, 2F,3G,3K,2L,3N,3P 4A 8A 7B, 5A 2H,10H 11H 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N 10R 11R 2R 1R 2A,7A,10A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F, 10F,1G,9G,10G,1J,2J,9J,1K,2K,9J,1L,9L,10L,1M,2M, 9M,1N,9N,10N,1P,2P,9P DESCRIPTION Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs Data Outputs Write Control Pin, active when low Read Control Pin, active when low Block Write Control Pin, active when low Input Reference Voltage Output Driver Impedance Control Input Power Supply (1.8 V) Output Power Supply (1.5V or 1.8V) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test Data Output No Connect 3 2 1 NOTE
Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 NC/SA* NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D2 NC NC VREF Q1 NC NC NC NC D8 TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC Q8 TDI
PIN CONFIGURATIONS(TOP VIEW) K7R320982C(4Mx9)
Notes: 1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 2A for 72Mb. 2. BW controls write to D0:D8.
PIN NAME
SYMBOL K, K C, C CQ, CQ Doff SA D0-8 Q0-8 W R BW VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO PIN NUMBERS 6B, 6A 6P, 6R 11A, 1A 1H 3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R 11M,11J,10E,11C,2D,2G,3L,2N,10P 11L,10J,11E,11B,3E,3G,2L,3P,11P 4A 8A 7B 2H,10H 11H 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N 10R 11R 2R 1R 2A,7A,5A,1B,2B,3B,5B,9B,10B,1C,2C,3C,9C,10C,1D,3D,9D,10D, 11D,1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,3J,9J 1K,2K,3K,10K,11K,9K,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N,9N 10N,11N,1P,2P,9P DESCRIPTION Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs Data Outputs Write Control Pin, active when low Read Control Pin, active when low Nibble Write Control Pin, active when low Input Reference Voltage Output Driver Impedance Control Input Power Supply (1.8 V) Output Power Supply (1.5V or 1.8V) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test Data Output 2 1 NOTE
NC
No Connect
3
Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
GENERAL DESCRIPTION
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
The K7R323682C,K7R321882C and K7R320982C are 37,748,736-bits QDR (Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 1,048,576 words by 36bits for K7R323682C, 2,097,152 words by 18 bits for K7R321882C and 4,194,304 words by 9bits for K7R320982C. The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle. Memory bandwidth is maximized as data can be transferred into SRAM on every rising edge of K and K, and transferred out of SRAM on every rising edge of C and C. And totally independent read and write ports eliminate the need for high speed bus turn around. Address, data inputs, and all control signals are synchronized to the input clock (K or K). Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high, the data outputs are synchronized to the input clocks (K and K). Read data are referenced to echo clock (CQ or CQ) outputs. Read address is registered on rising edges of the input K clocks, and write address is registered on rising edges of the input K clocks. Common address bus is used to access address both for read and write operations. The internal burst counter is fixed to 2-bit sequential for both read and write operations. Synchronous pipeline read and early write enable high speed operations. Simple depth expansion is accomplished by using R and W for port selection. Byte write operation is supported with BW0 and BW1 (BW2 and BW3) pins for x18 (x36) device and only BW pin for x9 device. IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system. The K7R323682C,K7R321882C and K7R320982C are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by activating R at the rising edge of the positive input clock K. Address is presented and stored in the read address register synchronized with K clock. For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 9-bit data words with each read command. The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge. Next burst data is triggered by the rising edge of following C clock rising edge. Continuous read operations are initiated with K clock rising edge. And pipelined data are transferred out of device on every rising edge of both C and C clocks. In case C and C tied to high, output data are triggered by K and K instead of C and C. When the R is disabled after a read operation, the K7R323682C,K7R321882C and K7R320982C will first complete burst read operation before entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state.
Write Operations
Write cycles are initiated by activating W at the rising edge of the positive input clock K. Address is presented and stored in the write address register synchronized with following K clock. For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 9-bit data words with each write command. The first "early" data is transferred and registered in to the device synchronous with same K clock rising edge with W presented. Next burst data is transferred and registered synchronous with following K clock rising edge. Continuous write operations are initiated with K rising edge. And "early write" data is presented to the device on every rising edge of both K and K clocks. When the W is disabled, the K7R323682C,K7R321882C and K7R320982C will enter into deselect mode. The device disregards input data presented on the same cycle W disabled. The K7R323682C, K7R321882C and K7R320982C support byte write operations. With activating BW0 or BW1 (BW2 or BW3) in write cycle, only one byte of input data is presented. In K7R321882C, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17. And in K7R323682C BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35. And in K7R320982C BW controls write operation to D0:D8.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
Single Clock Mode
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
K7R323682C,K7R321882C and K7R320982C can be operated with the single clock pair K and K, instead of C or C for output clocks. To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high during operation. After power up, this device can't change to or from single clock mode. System flight time and clock skew could not be compensated in this mode.
Depth Expansion
Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently and read and write operation do not affect each other. Before chip deselected, all read and write pending operations are completed.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor (RQ). The value of RQ (within 15%) is five times the output impedance desired. For example, 250 resistor will give an output impedance of 50. Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. To guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
Echo clock operation
To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are synchronized with internal data output. Echo clocks run free during normal operation. The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver.
Clock Consideration
K7R323682C,K7R321882C and K7R320982C utilizes internal DLL (Delay-Locked Loops) for maximum output data valid window. It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles. Circuitry automatically resets the DLL when absence of input clock is detected.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-down.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
Detail Specification of Power-Up Sequence in QDRII SRAM
QDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
* Power-Up Sequence
1. Apply power and keep Doff at low state (All other inputs may be undefined) - Apply VDD before VDDQ - Apply VDDQ before VREF or the same time with VREF 2. Just after the stable power and clock (K, K, C, C), take Doff to be high. 3. The additional 1024cycles of clock input is required to lock the DLL after enabling DLL * Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds (Min. 30ns) to reset the DLL after it become a stable clock status.
* DLL Constraints
1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as TKC var. 2. The lower end of the frequency at which the DLL can operate is 8.4ns. 3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency and this may cause the failure in the initial stage.
Power up & Initialization Sequence (Doff pin controlled)
~ ~~
K,K
1024 cycle DLL Locking Range
Inputs Clock must be stable
Status
Power-Up
Unstable CLKstage
~ ~~
Any Command
VDD VDDQ VREF Doff
Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)
~~ ~
K,K
Min. 30ns
~~
1024 cycle
~
~
Status VDD VDDQ VREF
Power-Up
Unstable CLKstage
~
Stop Clock
DLL Locking Range
Inputs Clock must be stable
Any Command
* Notes: When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 1024 cycles of clock input is needed to lock the DLL.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
K Stopped R X H L X W X H X L
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
D D(A0) Previous state X X Din at K(t) D(A1) Previous state X X Din at K(t) Q(A0) Previous state High-Z DOUT at C(t+1) X
Q Q(A1) Previous state High-Z DOUT at C(t+2) X
OPERATION Clock Stop No Operation Read Write
Notes: 1. X means "Dont Care". 2. The rising edge of clock is symbolized by ( ). 3. Before enter into clock stop status, all pending read and write operations will be completed.
WRITE TRUTH TABLE(x18)
K
Notes: 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ). 3. Assumes a WRITE cycle was initiated. 4. This table illustrates operation for x18 devices. x9 device operation is similar except that BW controls D0:D8.
K
BW0 L L L L H H H H
BW1 L L H H L L H H
OPERATION WRITE ALL BYTEs ( K) WRITE ALL BYTEs ( K) WRITE BYTE 0 ( K) WRITE BYTE 0 ( K) WRITE BYTE 1 ( K) WRITE BYTE 1 ( K) WRITE NOTHING ( K) WRITE NOTHING ( K)
WRITE TRUTH TABLE(x36)
K
Notes: 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ). 3. Assumes a WRITE cycle was initiated.
K
BW0 L L L L H H H H H H
BW1 L L H H L L H H H H
BW2 L L H H H H L L H H
BW3 L L H H H H L L H H
OPERATION WRITE ALL BYTEs ( K ) WRITE ALL BYTEs ( K ) WRITE BYTE 0 ( K ) WRITE BYTE 0 ( K ) WRITE BYTE 1 ( K ) WRITE BYTE 1 ( K ) WRITE BYTE 2 and BYTE 3 ( K ) WRITE BYTE 2 and BYTE 3 ( K ) WRITE NOTHING ( K) WRITE NOTHING ( K )
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to VSS Voltage on Input Pin Relative to VSS Storage Temperature Operating Temperature Storage Temperature Range Under Bias
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
SYMBOL VDD VDDQ VIN TSTG Commercial / Industrial TOPR TBIAS RATING -0.5 to 2.9 -0.5 to VDD -0.5 to VDD+0.3 -65 to 150 0 to 70 / -40 to 85 -10 to 85 UNIT V V V C C C
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation.
OPERATING CONDITIONS
PARAMETER Supply Voltage Reference Voltage SYMBOL VDD VDDQ VREF Min 1.7 1.4 0.68 MAX 1.9 1.9 0.95 UNIT V V V
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current Output Leakage Current Operating Current (x36) SYMBOL IIL IOL ICC TEST CONDITIONS VDD=Max; VIN=VSS to VDDQ Output Disabled, VDD=Max, IOUT=0mA Cycle Time tKHKH Min -30 -25 -20 -30 -25 -20 -30 -25 -20 -30 -25 -20 MIN -2 -2 MAX +2 +2 850 800 750 800 750 700 750 700 650 350 330 300 V V V V V V 2,7 3,7 4 4 8,9 8,10 mA 1,6 mA 1,5 mA 1,5 mA 1,5 UNIT NOTES A A
Operating Current (x18)
ICC
VDD=Max, IOUT=0mA Cycle Time tKHKH Min.
Operating Current (x9)
ICC
VDD=Max, IOUT=0mA Cycle Time tKHKH Min.
Standby Current (NOP) Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Input Low Voltage Input High Voltage
ISB1 VOH1 VOL1 VOH2 VOL2 VIL VIH
Device deselected, IOUT=0mA, f=Max, All Inputs0.2V or VDD-0.2V
VDDQ/2-0.12 VDDQ/2+0.12 VDDQ/2-0.12 VDDQ/2+0.12 IOH=-1.0mA IOL=1.0mA VDDQ-0.2 VSS -0.3 VREF+0.1 VDDQ 0.2 VREF-0.1 VDDQ+0.3
Notes: 1. Minimum cycle. IOUT=0mA. 2. |IOH|=(VDDQ/2)/(RQ/5)15% for 175 RQ 350. 3. |IOL|=(VDDQ/2)/(RQ/5)15% for 175 RQ 350. 4. Minimum Impedance Mode when ZQ pin is connected to VDD. 5. Operating current is calculated with 50% read cycles and 50% write cycles. 6. Standby Current is only after all pending read and write burst operations are completed. 7. Programmable Impedance Mode. 8. These are DC test criteria. DC design criteria is VREF50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 9. VIL (Min.) DC=-0.3V, VIL (Min.) AC=-1.5V(pulse width 3ns). 10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width 3ns).
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
PARAMETER Input High Voltage Input Low Voltage
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
SYMBOL VIH (AC) VIL (AC) MIN VREF + 0.2 MAX VREF - 0.2 UNIT V V NOTES 1,2 1,2
AC ELECTRICAL CHARACTERISTICS
Notes: 1. This condition is for AC function test only, not for AC parameter test. 2. To maintain a valid level, the transition edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC) b) Reach at least the target AC level c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
AC TIMING CHARACTERISTICS
PARAMETER Clock Clock Cycle Time (K, K, C, C) Clock Phase Jitter (K, K, C, C) Clock High Time (K, K, C, C) Clock Low Time (K, K, C, C) Clock to Clock (K K, C C) Clock to data clock (K C, K C) DLL Lock Time (K, C) K Static to DLL reset Output Times C, C High to Output Valid C, C High to Output Hold C, C High to Echo Clock Valid C, C High to Echo Clock Hold CQ, CQ High to Output Valid CQ, CQ High to Output Hold C, High to Output High-Z C, High to Output Low-Z Setup Times Address valid to K rising edge Control inputs valid to K rising edge Data-in valid to K, K rising edge Hold Times K rising edge to address hold K rising edge to control inputs hold K, K rising edge to data-in hold tKHAX tKHIX tKHDX 0.3 0.3 0.3 0.35 0.35 0.35 0.40 0.40 0.40 ns ns ns tAVKH tIVKH tDVKH 0.3 0.3 0.3 0.35 0.35 0.35 0.40 0.40 0.40 ns ns ns 2 tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 -0.45 -0.27 0.45 -0.45 -0.45 0.27 -0.30 0.45 -0.45 -0.45 0.45 -0.45 0.30 -0.35 0.45 0.45 -0.45 0.45 -0.45 0.35 0.45 -0.45 0.45 0.45 ns ns ns ns ns ns ns ns 7 7 3 3 3 3 tKHKH tKC var tKHKL tKLKH tKHKH tKHCH tKC lock tKC reset 1.32 1.32 1.49 0.00 1024 30 1.45 3.3 8.40 0.20 1.60 1.60 1.80 0.00 1024 30 1.80 4.00 8.40 0.20 2.00 2.00 2.20 0.00 1024 30 2.30 5.00 8.40 0.20 ns ns ns ns ns ns cycle ns 6 5 SYMBOL -30 MIN MAX MIN -25 MAX MIN -20 MAX UNITS NOTES
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control singles are R, W,BW0,BW1 and BW2, BW3, also for x36 3. If C,C are tied high, K,K become the references for C,C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. 7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a 0.1 ns variation from echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
THERMAL RESISTANCE
PRMETER Junction to Ambient Junction to Case Junction to Pins
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
SYMBOL JA JC JB Typ 20.8 2.3 4.3 Unit NOTES
C/W C/W C/W
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site thermal impedance. TJ=TA + PD x JA
PIN CAPACITANCE
PRMETER Address Control Input Capacitance Input and Output Capacitance Clock Capacitance SYMBOL CIN COUT CCLK TESTCONDITION VIN=0V VOUT=0V Typ 3.5 4 3 Max 4 5 4 Unit pF pF pF NOTES
Note: 1. Parameters are tested with RQ=250 and VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
AC TEST CONDITIONS
Parameter Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level
Note: Parameters are tested with RQ=250
AC TEST OUTPUT LOAD
Symbol VDD VDDQ VIH/VIL VREF TR/TF Value 1.7~1.9 1.4~1.9 1.25/0.25 0.75 0.3/0.3 VDDQ/2 Unit V V V V ns V
VREF 0.75V
VDDQ/2 50 Zo=50
SRAM
ZQ 250
Overershoot Timing
20% tKHKH(MIN) VDDQ+0.5V VDDQ+0.25V VDDQ
Undershoot Timing
VIH
VSS VSS-0.25V VSS-0.5V
VIL
Note: For power-up, VIH VDDQ+0.3V and VDD 1.7V and VDDQ 1.4V t 200ms
20% tKHKH(MIN)
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
APPLICATION INRORMATION
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
Vt R
Data In Data Out Address R W BW
D SA
CQ CQ Q R W BW0 BW1 C C K K
SRAM#1
ZQ R=250
R=250 CQ CQ Q RW BW0 BW1 C C K K SRAM#4 ZQ ZQ
D SA
R
Vt Vt
MEMORY CONTROLLER
Return CLK Source CLK Return CLK Source CLK
Vt Vt
R=50 Vt=VREF
SRAM1 Input CQ SRAM1 Input CQ SRAM4 Input CQ SRAM4 Input CQ
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
READ
tKHKH
TIMING WAVE FORMS OF READ AND NOP
READ
tKLKH tKHKH
NOP
READ
NOP
K
tKHKL
K
tAVKH tKHAX
SA
A1
tIVKH tKHIX
A2
A3
R
tCHQX1
Q (Data Out)
tKHKH tKLKH tKHCH
Q1-1
tCHQV
Q1-2
tCHQX
Q2-1
Q2-2
tCHQZ
Q3-1
C
tKHKL tKHKH
C
tCHQV tCHCQV tCQHQV tCHCQV tCQHQX tCHCQX
CQ
CQ
tCHCQX
Dont Care
2. Outputs are disabled one cycle after a NOP.
Undefined
Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
TIMING WAVE FORMS OF WRITE AND NOP
WRITE
tKHKH
WRITE
NOP
WRITE
NOP
K
tKHKL
tKLKH tKHKH
K
tAVKH tKHAX
SA
tIVKH tKHIX
A1
A2
A3
W
tKHIX
D (Data In)
D1-1
D1-2
D2-1
D2-2
D3-1
tDVKH
D3-2
tKHDX
Dont Care
Undefined
Note: 1.D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1, i.e the next internal burst address following A1+0. 2. BWx (NWx) assumed active.
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
TIMING WAVE FORMS OF READ, WRITE AND NOP
READ K WRITE READ WRITE READ WRITE NOP WRITE NOP
K
SA
A1
A2
A3
A4
A5
A6
A7
W
R
D (Data In)
D2-1
D2-2
D4-1
D4-2
D6-1
D6-2
D7-1
D7-2
Q (Data Out)
Q1-1
Q1-2
Q3-1
Q3-2
Q5-1
Q5-2
C
C
CQ
CQ
Dont Care
Note: 1. If address A1=A2, data Q1-1=D2-1, data Q1-2=D2-2. Write data is forwarded immediately as read results. 2.BWx (NWx) assumed active.
Undefined
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z RESERVED SAMPLE RESERVED RESERVED BYPASS TDO Output Boundary Scan Register Identification Register Boundary Scan Register Do Not Use Boundary Scan Register Do Not Use Do Not Use Bypass Register Notes 1 3 2 6 5 6 6 4
A,D K,K C,C Q CQ CQ TDI BYPASS Reg. Identification Reg. Instruction Reg. Control Signals TMS TCK TAP Controller TDO SRAM CORE
NOTE: 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use.
TAP Controller State Diagram
1 0 Test Logic Reset 0 Run Test Idle
1 1
Select DR 0 Capture DR 0 Shift DR 1 Exit1 DR 0 Pause DR 1 Exit2 DR 1 Update DR 0
1 1
Select IR 0 Capture IR
1
0
0 1 Shift IR 1 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 0
1
0 0
1
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
SCAN REGISTER DEFINITION
Part 1Mx36 2Mx18 4Mx9 Instruction Register 3 bits 3 bits 3 bits
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
Bypass Register 1 bit 1 bit 1 bit ID Register 32 bits 32 bits 32 bits Boundary Scan 109 bits 109 bits 109 bits
ID REGISTER DEFINITION
Part 1Mx36 2Mx18 4Mx9 Revision Number (31:29) 000 000 000 Part Configuration (28:12) 00def0wx0t0q0b0s0 00def0wx0t0q0b0s0 00def0wx0t0q0b0s0 Samsung JEDEC Code (11: 1) 00011001110 00011001110 00011001110 Start Bit(0) 1 1 1
Note: Part Configuration /def=010 for 36Mb, /wx=11 for x36, 10 for x18, 00 for x9. /t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
BOUNDARY SCAN EXIT ORDER
ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E ORDER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PIN ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 PIN ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal
Note: 1. NC pins are read as "X" (i.e. dont care.)
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
JTAG DC OPERATING CONDITIONS
Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(IOH=-2mA) Output Low Voltage(IOL=2mA) Symbol VDD VIH VIL VOH VOL Min 1.7 1.3 -0.3 1.4 VSS Typ 1.8 Max 1.9 VDD+0.3 0.5 VDD 0.4 Unit V V V V V Note
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level
Note: 1. See SRAM AC test output load on page 11.
Symbol VIH/VIL TR/TF
Min 1.8/0.0 1.0/1.0 0.9
Unit V ns V
Note
1
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min 50 20 20 5 5 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns ns ns Note
JTAG TIMING DIAGRAM
TCK
tCHCH tMVCH tCHMX
tCHCL
tCLCH
TMS
tDVCH tCHDX
TDI
tSVCH tCHSX
PI (SRAM)
tCLQV
TDO
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Rev. 1.1 August 2006
K7R323682C K7R321882C K7R320982C
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
165 FBGA PACKAGE DIMENSIONS (Lead & Lead-Free)
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
B
Top View
A C D
A G
Side View
E
B
F
Bottom View
H
E
Symbol A B C D
Value 15 0.1 17 0.1 1.3 0.1 0.35 0.05
Units mm mm mm mm
Note
Symbol E F G H
Value 1.0 14.0 10.0 0.5 0.05
Units mm mm mm mm
Note
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Rev. 1.1 August 2006

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